Clock signal generator circuits are utilized extensively in semiconductor memories. The clock signals generated by these circuits serve to sequence the operation of the memory. A clock signal frequently must drive a heavy capacitive load while maintaining a rapid transition rate. The driver transistors for such clock circuits must therefore be relatively large. The timing in the operation of conventional clock circuits can cause an overlap in the turn-on of the driver transistors, thereby creating a heavy current spike which can be detrimental to the circuit. This is often the result when capacitive bootstrapping is used to produce a high voltage drive signal for the output transistors.
In view of the above problems there exists a need for a clock circuit which can produce a desired clock signal with a rapid transition rate but prevents the occurrence of current spikes through the clock circuit.